Semiconductor device
AssigneeToshiba Memory Corporation
InventorsTakao SUEYAMA, Keiko KANEDA, Tomoko FUJIWARA
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Abstract
A semiconductor memory device includes an n-type source/drain formed in a surface region of a p-type active region, and a gate. The semiconductor memory device also includes a withstand voltage improvement layer provided with a preset distance maintained from at least one end of the source/drain. N-type impurities are diffused in the withstand voltage improvement layer, and a withstand voltage improvement voltage is applied to the withstand voltage improvement layer to expand a depletion layer to reach the source/drain, so that the maximum withstand voltage value of a transistor is increased.
Claims12
A semiconductor device comprising:
- a first semiconductor region serving as an active region of first conductivity type;
- a second semiconductor region and a third semiconductor region which are provided in a surface region of the first semiconductor region and which are away from each other, impurities of second conductivity type being diffused in the second semiconductor region and impurities of the second conductivity type being diffused in the third semiconductor region;
- a control electrode arranged between the second semiconductor region and the third semiconductor region and provided on the first semiconductor region via an insulating layer;
- and
- a fourth semiconductor region which is arranged in the first semiconductor region to be away from at least one end of the second semiconductor region and the third semiconductor region by a predetermined distance, impurities of the second conductivity type being diffused in the fourth semiconductor region, a depletion layer being expanded to reach the second semiconductor region or the third semiconductor region from the fourth semiconductor region by applying a voltage to the fourth semiconductor region.
Dependencies are inferred from the claim text.