Array substrate and manufacturing method thereof, and dislay device

A method of manufacturing an array substrate, comprising:

• forming a first active layer, a second active layer and a target conductive layer on a base substrate, to obtain a first transistor and a second transistor, wherein an orthographic projection of the first transistor on the base substrate and an orthographic projection of the second transistor on the base substrate are non-overlapped;
• the first transistor comprises:
• a first active layer, a first gate, a first source and a first drain, wherein the first source and the first drain are in a same layer and are both in contact with the first active layer;
• the second transistor comprises:
• a second active layer, a second gate, a second source and a second drain, wherein the second source and the second drain are on a side, close to the base substrate, of the second active layer, are both in contact with the second active layer, and the second source and the second drain are in different layers, an orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap, and the second gate is on a side, away from the base substrate, of the second active layer;
• and
• the target conductive layer comprises:
• at least one of a first conductive pattern, a second conductive pattern and a third conductive pattern, wherein each conductive pattern in the target conductive layer is formed by a single patterning process after formation of a material layer, the first conductive pattern comprises:
• one of the second source and the second drain, as well as the first gate;
• the second conductive pattern comprises:
• the first source and the first drain, as well as the other one of the second source and the second drain;
• and the third conductive pattern comprises:
• the second gate.

A display device, comprising:

• an array substrate, wherein the array substrate comprises:
• a base substrate, and a first transistor and a second transistor on a side of the base substrate;
• wherein
• an orthographic projection of the first transistor on the base substrate and an orthographic projection of the second transistor on the base substrate are non-overlapped:
• the first transistor comprises:
• a first active layer, a first gate, a first source and a first drain, wherein the first source and the first drain are in a same layer and are both in contact with the first active layer;
• the second transistor comprises:
• a second active layer, a second gate, a second source and a second drain, wherein the second source and the second drain are on a side, close to the base substrate, of the second active layer, and are both in contact with the second active layer, and the second source and the second drain are in different layers;
• an orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap;
• and the second gate is on a side, away from the base substrate, of the second active layer;
• and
• structures in the first transistor and the second transistor meet at least one of following conditions:
• the first gate, and one of the second source and the second drain are in a layer and made from a same material;
• the first source, the first drain and the other one of the second source and the second drain are in a same layer and made from a same material.