Methods of forming metal on inhomogeneous surfaces and structures incorporating metal on inhomogeneous surfaces
AssigneeMicron Technology, Inc.
InventorsTsz Wah Chan, Yongjun J. Hu, Swapnil Lengade
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Abstract
The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.
Claims20
A method of forming an integrated circuit, comprising:
- forming a lower conductive line stack comprising a first seeding line extending in a first direction;
- forming an upper conductive line stack n contact with and across a substantially planar top surface of a second seeding line, the upper conductive line stack comprising tungsten, the second seeding line extending in a second direction different than the first direction, a bottom surface of the second seeding line in contact with a carbon electrode surface and in contact with an insulator surface extending in the first direction, wherein a sidewall of the second seeding line is in contact with a second insulator surface extending in the second direction;
- and
- forming a phase change memory cell stack comprising a chalcogenide element positioned above the lower conductive line stack and below the upper conductive line stack.
A method of forming a memory device, comprising:
- forming a memory deck, including:
- forming a first plurality of conductive lines extending in a first direction;
- forming a second plurality of conductive lines extending in a second direction different than the first direction;
- forming a plurality of first seeding lines comprising an amorphous silicon material below the second plurality of conductive lines and extending in the second direction, the plurality of first seeding lines having a substantially planar top surface and the second conductive lines being in contact with and formed across the substantially planar upper surface of the plurality of first seeding lines, a bottom surface of the plurality of first seeding lines in contact with a corresponding electrode surface of a plurality of electrode surfaces and a corresponding insulator surface of a plurality of insulator surfaces extending in the first direction;
- and
- forming a first plurality of memory cell stacks between the first plurality of conductive lines and the plurality of first seeding lines, wherein each memory cell stack of the first plurality of memory cell stacks comprises a chaicogenide element, a carbon electrode interposing the chalcogenide element and a first seeding line, and the carbon electrode in contact with the seeding line.
The method of claim 15, wherein the second plurality of conductive lines is shared between the memory deck and the additional memory deck.
A method of forming memory cell, comprising:
- forming a first conductive line extending in a first direction;
- forming a second conductive line disposed above a seeding line formed of a seeding material comprising an amorphous silicon material, the second conductive line comprising tungsten, the second conductive line extending in a second direction and crossing the first conductive line, the second direction different than the first direction, the seeding line having a substantially planar top surface, a bottom surface of the seeding line in contact with an electrode surface and a first insulator surface in the first direction, wherein a sidewall of the seeding line is in contact with a second insulator surface in the second direction, and the second conductive line being in contact with and formed across the substantially planar top surface of the seeding line, the substantially planar top surface having a local step height variation thickness of about 5 nm, the tungsten having a resistivity based at least in part on a grain size distribution, the grain size distribution being based at least in part on the seeding line having the substantially planar top surface and a thickness of the seeding line;
- forming a chalcogenide element between the first and second conductive lines, wherein the seeding line is interposed between the second conductive line and the chalcogenide element, the seeding line contacting the second conductive line;
- and
- forming a carbon electrode between the chalcogenide element and the seeding line, the carbon electrode in contact with the seeding line.
Dependencies are inferred from the claim text.