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US 2020/0091240 A1Published application
Memory device having puc structure
AssigneeSK hynix Inc.
InventorJi-Hoon HONG
Life of this patent
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Abstract
A memory device includes first and second peripheral regions in which peripheral circuits related to data input/output are disposed, a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed, and a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed.
Claims23
A memory device comprising:
- first and second peripheral regions in which peripheral circuits related to data input/output are disposed;
- a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed;
- and
- a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed.
1 more element
A memory device comprising:
- a peripheral region including a plurality of lower metal wiring layers formed on a substrate;
- first and second upper metal wiring layers disposed on the peripheral region;
- a normal cell region disposed on the first upper metal wiring layer, coupled to the first upper metal wiring layer through a contact, and including a plurality of normal cells storing data;
- and
- a dummy cell region disposed on the second upper metal wiring layer, coupled to the second upper metal wiring layer through a contact, and including a plurality of dummy cells forming a plurality of capacitors.
2 more elements
A memory device comprising:
- first and second resistive cell arrays disposed in parallel on a substrate;
- and
- first and second peripheral circuits disposed under the first and second resistive cell arrays, respectively,
- wherein the first and second peripheral circuits exchange signals with the first resistive cell array to store data, and
- wherein the second resistive cell array includes a plurality of capacitors formed between word lines and bit lines thereof.
2 more elements
Dependencies are inferred from the claim text.