US 2020/0091239 A1Published application

Semiconductor device

AssigneeToshiba Memory Corporation

InventorTakayuki MIYAZAKI

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Abstract

A semiconductor device includes a plurality of first conductive lines in a first wiring layer, a plurality of second conductive lines in a second wiring layer, and a plurality of memory cells between the first and second conductive lines in a first direction in a first region. A plurality of third conductive lines in the first wiring layer, a plurality of fourth conductive lines in the second wiring, and a plurality of first memory lines are in a second region. The third conductive lines extends in a second direction and are spaced from each other in a third direction. The fourth conductive lines extend in the second direction and are spaced in the third direction. The first memory lines are between the third conductive lines and the fourth conductive lines in the first direction. The first memory lines comprise the same materials as the memory cells.

Claims20

Dependent claims

A semiconductor device, comprising:

a first region on a substrate;
a second region on the substrate;
a first wiring layer on the substrate in both the first region and the second region;
a second wiring layer on the substrate in both the first region and the second region;
a first memory cell layer between the first and second wiring layers in a first direction orthogonal to the substrate;
a plurality of first conductive lines in the first wiring layer in the first region and extending in a second direction that is parallel to the substrate, the first conductive lines being spaced from each other in a third direction crossing the second direction and parallel to the substrate;
a plurality of second conductive lines in the second wiring layer in the first region and extending in the third direction and spaced from each other in the second direction;
a first plurality of memory cells in the first memory cell layer in the first region respectively between a first conductive line and a second conductive line at a crossing point of the first conductive line and the second conductive line;
a plurality of third conductive lines in the first wiring layer in the second region and extending in the second direction and spaced from each other in the third direction;
a plurality of fourth conductive lines in the second wiring layer in the second region and extending in the second direction and spaced from each other in the third direction;
a first plurality of memory lines in the first memory cell layer in the second region respectively between a third conductive line and a fourth conductive line, the memory lines extending coextensively in the second direction with the third and fourth conductive lines, wherein
the memory cells and the memory lines in the first memory cell layer are comprised of same materials, and
a capacitor element is formed in the second region by the plurality of third conductive lines, the plurality of fourth conductive lines, and the first plurality of memory lines.

10 more elements

A semiconductor device, comprising:

a memory region on a substrate;
a peripheral region on the substrate adjacent to the memory region;
a plurality of bit lines in a first wiring level in the memory region, the bit lines extending in a first direction and spaced from each other in a second direction;
a plurality of word lines in a second wiring level in the memory region, the word lines extending in the second direction and spaced from each other in the first direction;
a first plurality of memory cells between the first and second wiring levels in the memory region in a third direction orthogonal to the substrate, each memory cell respectively being at a crossing point of a bit line and a word line;
a plurality of first conductive lines in the first wiring level in the peripheral region, the first conductive lines extending in the first direction and spaced from each other in the second direction;
a plurality of second conductive lines in the second wiring level in the peripheral region, the second conductive lines extending in the first direction and spaced from each other in the second direction;
a first plurality of memory lines in the peripheral region between the first and second wiring levels in the third direction, each memory line being between a third conductive lines and a fourth conductive line and extending coextensively in the first direction with the third and fourth conductive lines, wherein
the memory cells and the memory lines are comprised of same materials, and
a capacitor element is formed in the peripheral region by the plurality of first conductive lines, the plurality of second conductive lines, and the first plurality of memory lines.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/290,406Filed 1 Mar 2019
Priority: JP 2018-17425218 Sep 2018
Published: 19 Mar 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification30 codes

H10B 63/80
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: arrangements comprising multiple bistable or multi-stable switching…
G01R 31/2884
Testing of integrated circuits [IC]: using dedicated test connectors, test elements or test circuits on the IC under test
G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 11/1653
Auxiliary circuits: address circuits or decoders