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US 2020/0091232 A1Published application
Shared Three-Dimensional Vertical Memory
AssigneeHangZhou HaiCun Information Technology Co., Ltd.
InventorGuobiao ZHANG
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Abstract
In a shared three-dimensional vertical memory (3D-MV), each horizontal address line comprises at least two regions: a lightly-doped region and a low-resistivity region. The lightly-doped region is formed around selected memory holes and shared by a plurality of low-leakage memory cells. The low-resistivity region forms a conductive network to reduce the resistance of the horizontal address line.
Claims20
A three-dimensional vertical memory (3D-MV), comprising:
- a semiconductor substrate including a substrate circuit;
- a plurality of horizontal address lines stacked above said substrate circuit;
- a plurality of memory holes penetrating through said horizontal address lines;
- a plurality of programmable layers covering the sidewalls of said memory holes;
- a plurality of vertical address lines formed in said memory holes;
- each of said horizontal address lines including at least a first region and a second region outside said first region, wherein:
- said first region comprises at least a lightly-doped semiconductor material surrounding selected ones of said memory holes;
- said first region has a higher resistivity than said second region;
- and,
- a first plurality of said memory holes penetrate through said first region;
- a second plurality of said memory holes penetrate through said second region.
8 more elements
A three-dimensional vertical memory (3D-MV), comprising:
- a semiconductor substrate including a substrate circuit;
- a plurality of horizontal address lines stacked above said substrate circuit;
- a plurality of memory holes penetrating through said horizontal address lines;
- a plurality of programmable layers covering the sidewalls of said memory holes;
- a plurality of vertical address lines formed in said memory holes;
- each of said horizontal address lines including at least a first region and a second region outside said first region, wherein:
- said first region comprises at least a lightly-doped semiconductor material surrounding selected ones of said memory holes;
- said first region has a higher resistivity than said second region;
- and,
- said memory holes penetrate through said first region;
- none of said memory holes penetrate through said second region.
8 more elements
Dependencies are inferred from the claim text.