Semiconductor structure and manufacturing method of the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsALEXANDER KALNITSKY, SHENG-HUANG HUANG, HARRY-HAK-LAY CHUANG, JIUNYU TSAI, HUNG CHO WANG
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Abstract
The present disclosure provides a semiconductor structure having a memory region. The semiconductor structure includes an Nth metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region, a plurality of magnetic tunneling junctions (MTJs) over the Nth metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via over each of the plurality of MTJs; and an (N+M)th metal layer over the plurality of MTJs. A method for manufacturing the semiconductor structure is also disclosed.
Claims20
A semiconductor structure, comprising:
- a memory region, comprising:
- an Nth metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region;
- a plurality of magnetic tunneling junctions (MTJs) over the Nth metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes;
- a top electrode via over each of the plurality of MTJs;
- and
- an (N+M)th metal layer over the plurality of MTJs,
- wherein N is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.
A method for manufacturing a semiconductor structure, the method comprising:
- forming an Nth metal layer in a memory region and in a periphery region;
- forming a plurality of magnetic tunneling junctions (MTJs) in the memory region, the plurality of MTJs having at least one of mixed pitches and mixed sizes;
- forming a planarization etch stop layer in the memory region and in the periphery region;
- and
- performing an etch back operation until a portion of the planarization etch stop layer in the memory region is removed,
- wherein N is an integer greater than or equal to 1.
A method for manufacturing a semiconductor structure, the method comprising:
- forming a plurality of magnetic tunneling junctions (MTJs) in a memory region, the plurality of MTJs having at least one of mixed pitches and mixed sizes;
- forming an oxide layer in the memory region over the plurality of MTJs and in a periphery region adjacent to the memory region;
- forming a planarization etch stop layer over the oxide layer;
- and
- performing an etch back operation until a portion of oxide layer in the memory region is exposed.
Dependencies are inferred from the claim text.