Semiconductor package and method of manufacturing the same

A semiconductor package, comprising:

• a first redistribution layer having opposite upper and lower sides, the first redistribution layer comprising a first body of dielectric material and redistribution wiring including a layer of electrically conductive patterns within the first body of dielectric material;
• a first semiconductor chip disposed on the lower side of the first redistribution layer and electrically connected to the redistribution wiring of the first redistribution layer;
• a second semiconductor chip disposed on the upper side of the first redistribution layer and electrically connected to the redistribution wiring of the first redistribution layer;
• a molding layer on the upper side of the first redistribution layer and encapsulating the second semiconductor chip on the first redistribution layer;
• electrically conductive pillars each extending axially through the molding layer laterally of the second semiconductor chip and electrically connected to the redistribution wiring of the first redistribution layer;
• a second redistribution layer on the molding layer, the second redistribution layer comprising a second body of dielectric material and redistribution wiring including a layer of electrically conductive patterns within the second body of dielectric material, the redistribution wiring of the second redistribution layer being electrically connected to the pillars;
• and
• a third semiconductor chip on the second redistribution layer, the third semiconductor chip having chip pads facing the second redistribution layer and electrically connected to the redistribution wiring of the second redistribution layer,
• wherein, when viewed in plan, the third semiconductor chip overlaps the second semiconductor chip and the pillars.

A semiconductor package, comprising:

• a first layer including a first semiconductor chip;
• a second layer stacked on the first layer and including a second semiconductor chip, a molding layer encapsulating the second semiconductor chip;
• a third layer stacked on the second layer and including a third semiconductor chip;
• a first redistribution layer interposed between the first layer and the second layer, the first redistribution layer comprising a first body of dielectric material and redistribution wiring including a layer of electrically conductive patterns within the first body of dielectric material;
• a second redistribution layer interposed between the second layer and the third layer, the second redistribution layer comprising a second body of dielectric material and redistribution wiring including a layer of electrically conductive patterns within the second body of dielectric material;
• and
• electrically conductive pillars extending axially through the molding layer laterally of the second semiconductor chip,
• wherein when viewed in plan, the third semiconductor chip overlaps the second semiconductor chip and the pillars,
• the molding layer is sandwiched between the first body of dielectric material and the second body of dielectric material,
• the redistribution wiring of the second redistribution layer electrically connects the third semiconductor chip to the pillars,
• the redistribution wiring of the first redistribution layer electrically connects to first semiconductor chip to the pillars, and
• the redistribution wiring of one of the first and second redistribution layers electrically connects the second semiconductor chip to the pillars.