US 2020/0091202 A1Published application

Display device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsShunpei YAMAZAKI, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Tomoya Futamura, Takahiro Kasahara

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Abstract

A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

Claims7

Dependent claims

A display device comprising:

a pixel portion comprising a pixel electrode;
a common wiring;
a protective circuit comprising a first thin film transistor, a second thin film transistor and a third thin film transistor;
and
a terminal portion configured to be connected to an FPC,
wherein the first thin film transistor includes:
a first gate electrode;
a first gate insulating layer over the first gate electrode;
a first oxide semiconductor layer over the first gate electrode with the first gate insulating layer interposed therebetween;
a first conductive layer in contact with the first oxide semiconductor layer and connected to the pixel portion;
and
a second conductive layer in contact with the first oxide semiconductor layer and connected to the common wiring,
wherein the second thin film transistor includes:
a second gate electrode connected to the pixel portion;
a second gate insulating layer over the second gate electrode;
a second oxide semiconductor layer over the second gate electrode with the second gate insulating layer interposed therebetween:
a third conductive layer in contact with the second oxide semiconductor layer and connected to the pixel portion;
and
a fourth conductive layer in contact with the second oxide semiconductor layer and connected to the first gate electrode,
wherein the third thin film transistor includes:
a third gate electrode connected to the common wiring;
a third gate insulating layer over the third gate electrode;
a third oxide semiconductor layer over the third gate electrode with the third gate insulating layer interposed therebetween;
a fifth conductive layer in contact with the third oxide semiconductor layer and connected to the first gate electrode;
and
a sixth conductive layer in contact with the third oxide semiconductor layer and connected to the common wiring,
wherein the terminal portion includes:
a seventh conductive layer formed using a same conductive layer as the first to sixth conductive layers;
and
an eighth conductive layer formed using a same conductive layer as the pixel electrode.

27 more elements

A display device comprising:

a protective circuit;
a pixel;
and
a terminal portion,
wherein the protective circuit includes a first transistor,
wherein the pixel includes a second transistor and a pixel electrode,
wherein the terminal portion includes a first conductive layer, a second conductive layer over the first conductive layer, and an FPC,
wherein the first transistor comprises:
a first gate electrode;
a gate insulating layer;
a first oxide semiconductor layer overlapping with the first gate electrode with the gate insulating layer interposed therebetween;
a first source electrode electrically connected to the first oxide semiconductor layer;
and
a first drain electrode electrically connected to the first oxide semiconductor layer,
wherein the second transistor comprises:
a second gate electrode;
the gate insulating layer;
a second oxide semiconductor layer overlapping with the second gate electrode with the gate insulating layer interposed therebetween;
a second source electrode electrically connected to the second oxide semiconductor layer;
and
a second drain electrode electrically connected to the second oxide semiconductor layer,
wherein the pixel electrode is electrically connected to one of the second source electrode and the second drain electrode,
wherein an insulating layer is positioned over the first oxide semiconductor layer and the second oxide semiconductor layer,
wherein the insulating layer includes oxygen,
wherein the first conductive layer, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are formed using a same conductive layer,
wherein the second conductive layer and the pixel electrode are formed using a same conductive layer, and
wherein the FPC is electrically connected to the first conductive layer through the second conductive layer.

24 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/690,804Filed 21 Nov 2019
Priority: JP 2008-24164519 Sep 2008
Published: 19 Mar 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
G02F 1/136204
Active matrix addressed cells: arrangements to prevent high voltage or static electricity failures
G02F 1/136286
Active matrix addressed cells: wiring, e.g. gate line, drain line
H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate

Family

Application12/556,704Continuation · filed 10 Sep 2009
Application14/700,562Division · filed 30 Apr 2015
Application16/690,804Division
Application14/700,562Continuation
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From the US filing history. Foreign family members aren’t listed.