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US 2020/0091201 A1Published application
Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHideki MATSUKURA
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Abstract
Two dual-gate transistors, which are electrically connected in parallel and provided in a compact design, are disclosed.
Claims7
A semiconductor device comprising:
- a first conductive layer;
- a first insulating layer over the first conductive layer;
- an oxide semiconductor layer over the first insulating layer;
- a second conductive layer over the oxide semiconductor layer;
- a third conductive layer over the oxide semiconductor layer;
- a second insulating layer over the second conductive layer and the third conductive layer;
- a fourth conductive layer over the second insulating layer;
- a fifth conductive layer over the second insulating layer;
- a third insulating layer over the fourth conductive layer and the fifth conductive layer;
- and
- a sixth conductive layer over the third insulating layer,
- wherein the oxide semiconductor layer includes a first channel formation region of a first transistor,
- wherein the oxide semiconductor layer includes a second channel formation region of a second transistor, and
- wherein the first conductive layer includes a region functioning as a first gate electrode of the first transistor and a region functioning as a second gate electrode of the second transistor.
11 more elements
Dependencies are inferred from the claim text.