Array substrates, display panels, and display apparatuses

An array substrate, comprising:

• a first signal line;
• a second signal line;
• a first Thin Film Transistor (TFT) electrically connected to the first signal line and the second signal line;
• and
• a second TFT electrically connected to the first signal line and the second signal line;
• wherein the first TFT comprises:
• a first conductive layer;
• and
• a second conductive layer configured to be electrically connected to the first conductive layer through a first via hole and to be at least partly overlapped with the first conductive layer, wherein the first via hole is located in a first region where the second conductive layer is overlapped with the first conductive layer;
• and
• wherein the second TFT comprises:
• a third conductive layer;
• and
• a fourth conductive layer configured to be electrically connected to the third conductive layer through a second via hole and to be at least partly overlapped with the third conductive layer, wherein the second via hole is located in a second region where the fourth conductive layer is overlapped with the third conductive layer;
• wherein the first conductive layer is connected to the first signal line, and the third conductive layer is connected to the second signal line,
• wherein the first TFT has a gate located in the first conductive layer, a source located in the second conductive layer, and a drain located in the fourth conductive layer, and
• wherein the second TFT has a gate located in the third conductive layer, a drain located in the second conductive layer, and a source located in the fourth conductive layer.