Semiconductor device including multi-stack structure

A semiconductor device comprising:

• a substrate having a cell region and a connection region adjacent to the cell region;
• a lower stack structure including a plurality of lower insulating layers and a plurality of lower interconnection layers, the plurality of lower insulating layers and the plurality of lower interconnection layers being alternately stacked on each other on the substrate, each of the plurality of lower interconnection layers including,
• a lower gate electrode portion in the cell region, and
• a lower extension line portion in the connection region, the lower extension line portion extending from the lower gate electrode portion;
• an upper stack structure including a plurality of upper insulating layers and a plurality of upper interconnection layers, the plurality of upper insulating layers and the plurality of upper interconnection layers being alternately stacked on each other on the lower stack structure, each of the plurality of upper interconnection layers including,
• an upper gate electrode portion in the cell region, and
• an upper extension line portion in the connection region, the upper extension line portion extending from the upper gate electrode portion, a first distance between the lower extension line portion included in an uppermost one of the plurality of lower interconnection layers and the upper extension line portion included in a lowermost one of the plurality of upper interconnection layers being less than a second distance between the lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and the upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers;
• and
• a channel structure passing through the upper stack structure and the lower stack structure.