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US 2020/0091181 A1Published application
Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorSatoshi NAGASHIMA
Life of this patent
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Abstract
A semiconductor memory device comprises: stacked bodies adjacent to each other in a second direction, each comprising conductive layers stacked in a first direction; semiconductor portions arranged in a third direction between the stacked bodies, and comprising semiconductor layers facing the conductive layers, and a first insulating layer; and a second insulating layer provided between the semiconductor portions. The smallest distance from a geometrical center of gravity of the second insulating layer to the stacked body on a predetermined first cross-section being represented by D1; a distance from surfaces of the stacked bodies facing the semiconductor portion on a predetermined second cross-section being represented by D2, the relationship 2D1>D2 is satisfied.
Claims13
A semiconductor memory device comprising:
- a substrate;
- a first stacked body comprising a plurality of first conductive layers stacked in a first direction intersecting with a surface of the substrate;
- a second stacked body comprising a plurality of second conductive layers stacked in the first direction, and being adjacent to the first stacked body in a second direction intersecting with the first direction;
- a plurality of semiconductor portions provided between the first stacked body and the second stacked body and arranged in a third direction intersecting with the first and second directions, the plurality of semiconductor portions comprising a first semiconductor layer facing the plurality of first conductive layers, a second semiconductor layer facing the plurality of second conductive layers, and a first insulating layer provided between the first semiconductor layer and the second semiconductor layer;
- a first memory portion storing information between the first conductive layer and the first semiconductor layer;
- a second memory portion storing information between the second conductive layer and the second semiconductor layer;
- and
- a second insulating layer provided between the semiconductor portions adjacent to each other in the third direction,
- wherein the width in the second direction of the first insulating layer has local maxima at a first position in the first direction and a second position in the first direction different from the first position,
- wherein, referring to a cross-section which intersects with the first direction and on which a width in the second direction of at least one of the first insulating layers is the smallest in the range between the first and second positions as a first cross-section;
- the smallest distance from a geometrical center of gravity of the second insulating layer to the first or second stacked body on the first cross-section being represented by D1;
- referring to a cross-section which intersects with the first direction and on which a width in the second direction of at least one of the first insulating layers is the largest as a second cross-section;
- a distance from a surface of the first stacked body facing a predetermined one of the semiconductor portions to a surface of the second stacked body facing the predetermined one of the semiconductor portions on the second cross-section being represented by D2,
- a relationship 2D1>D2 is satisfied.
11 more elements
A semiconductor memory device comprising:
- a substrate;
- a first stacked body comprising a plurality of first conductive layers stacked in a first direction intersecting with a surface of the substrate;
- a second stacked body comprising a plurality of second conductive layers stacked in the first direction, and being adjacent to the first stacked body in a second direction intersecting with the first direction;
- a plurality of semiconductor portions provided between the first stacked body and the second stacked body and arranged in a third direction intersecting with the first and second directions, the plurality of semiconductor portions comprising a first semiconductor layer facing the plurality of first conductive layers, a second semiconductor layer facing the plurality of second conductive layers, and a first insulating layer provided between the first semiconductor layer and the second semiconductor layer;
- a first memory portion storing information between the first conductive layer and the first semiconductor layer;
- a second memory portion storing information between the second conductive layer and the second semiconductor layer;
- and
- a second insulating layer provided between the semiconductor portions adjacent to each other in the third direction,
- wherein the first insulating layer comprises a first insulating portion extending in the first direction, and a second insulating portion extending in the first direction farther from the substrate than the first insulating portion, and
- the second insulating layer comprises a third insulating portion extending in the first direction, and a fourth insulating portion extending in the first direction farther from the substrate than the third insulating portion,
- wherein, referring to a distance between a center position in the second direction of the first insulating portion and a center position in the second direction of the second insulating portion as d1,
- referring to a distance between the center position in the second direction of the second insulating portion and a center position in the second direction of the fourth insulating portion as d2,
- the relationship d1>d2 is satisfied.
10 more elements
Dependencies are inferred from the claim text.