Memory system and semiconductor memory device

A semiconductor memory device comprising:

• a plurality of first interconnection layers stacked in a first direction;
• a plurality of second interconnection layers stacked in the first direction, the second interconnection layers respectively disposed apart from one of the first interconnection layers in a second direction intersecting the first direction;
• a semiconductor pillar provided between the first interconnection layers and the second interconnection layers, and extending in the first direction;
• a first charge storage layer disposed between the first interconnection layers and the semiconductor pillar;
• and
• a second charge storage layer disposed between the second interconnection layers and the semiconductor pillar, and
• wherein an operation in a first mode or in a second mode is executed, in the first mode, a third interconnection layer among the first interconnection layers is selected independently with a fourth interconnection layer among the second interconnection layers disposed apart in the second direction from the third interconnection layer, in the second mode, a fifth interconnection layer among the first interconnection layers, and sixth interconnection layer among the second interconnection layers disposed apart in the second direction from the fifth interconnection layer are selected in a batch.

A semiconductor memory device comprising:

• a plurality of first interconnection layers stacked in a first direction;
• a plurality of second interconnection layers stacked in the first direction;
• the second interconnection layers respectively disposed apart from one of the first interconnection layers in a second direction intersecting the first direction;
• a semiconductor pillar provided between the first interconnection layers and the second interconnection layers, and extending in the first direction;
• a first charge storage layer disposed between the first interconnection layers and the semiconductor pillar;
• and
• a second charge storage layer disposed between the second interconnection layers and the semiconductor pillar,
• wherein a third interconnection layer among the first interconnection layers is selected independently with a fourth interconnection layer among the second interconnection layers disposed apart in the second direction from the third interconnection layer, and
• a fifth interconnection layer among the first interconnection layers, and sixth interconnection layer among the second interconnection layers disposed apart in the second direction from the fifth interconnection layer are selected in a batch.