Semiconductor memory device and method for controlling semiconductor memory device

A semiconductor memory device comprising:

• a plurality of conductive layers including a first conductive layer to an nth conductive layer stacked in a first direction;
• a first semiconductor region of a first conductive type and having a first conductive impurity concentration;
• a second semiconductor region of a second conductive type and having a second conductive impurity concentration, the second semiconductor region closer to the nth conductive layer than the first semiconductor region;
• a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, extending in the n conductive layers, and having an impurity concentration lower than the first conductive impurity concentration of the first semiconductor region and the second conductive impurity concentration of the second semiconductor region;
• a plurality of charge storage regions from a first charge storage region to an nth charge storage region provided between the conductive layers and the semiconductor layer;
• and
• a control circuit configured to read data based on a charge amount in an sth charge storage region, among the plurality of charge storage regions, in a state where the semiconductor layer below an sth (1≤s≤n−1) conductive layer is the second conductive type and the semiconductor layer below an (s+1)th conductive layer is the first conductive type,
• wherein at the time of reading the data based on the charge amount in the sth charge storage region, a (s+1)th charge storage region is in a state where charges are not stored.

A method for controlling a semiconductor memory device, the method comprising:

• providing a plurality of conductive layers from a first to an nth conductive layer stacked in a first direction;
• providing a first semiconductor region of a first conductive type and having a first conductive impurity concentration;
• providing a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region, the second semiconductor region having a second conductive impurity concentration;
• providing a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, extending in the n conductive layers, and having an impurity concentration lower than the first conductive impurity concentration of the first semiconductor region and the second conductive impurity concentration of the second semiconductor region;
• providing a plurality of charge storage regions from a first to an nth charge storage region provided between the n conductive layers and the semiconductor layer;
• and
• preventing storing charges in at least one charge storage region among the charge storage regions.