Semiconductor memory device

A semiconductor memory device comprising:

• a first memory cell capable of holding data;
• a second memory cell capable of holding data;
• a first word line coupled to the first memory cell;
• a second word line coupled to the second memory cell;
• and
• a first bit line capable of being electrically coupled to both the first memory cell and the second memory cell,
• wherein the first memory cell shares a semiconductor layer with the second memory cell, and faces the second memory cell across the semiconductor layer,
• the device is configured to execute a first operation, a second operation, a third operation, a fourth operation, a fifth operation, and a sixth operation to erase data, wherein
• in the first operation, a first voltage is applied to the first word line, and a second voltage higher than the first voltage is applied to the semiconductor layer;
• in the second operation, the first voltage is applied to the second word line, and the second voltage is applied to the semiconductor layer;
• in the third operation after the first operation, a third voltage lower than the second voltage is applied to the first word line to read data from the first memory cell;
• in the fourth operation after the second operation, the third voltage is applied to the second word line to read data from the second memory cell;
• in the fifth operation after the third operation, a fourth voltage lower than the third voltage is applied to the first word line to read data from the first memory cell;
• and
• in the sixth operation after the fourth operation, the fourth voltage is applied to the second word line to read data from the second memory cell.