Single-poly non-volatile memory cell and operating method thereof

A non-volatile memory array, comprising:

• a plurality of non-volatile memory cells, comprising at least a first non-volatile memory cell, a second non-volatile memory cell, a third non-volatile memory cell, and a fourth non-volatile memory cell, wherein each of the non-volatile memory cells comprises:
• a floating-gate transistor, deposited in a P-well and comprising a gate terminal, a drain terminal, and a source terminal, wherein the gate terminal is coupled to a floating gate, the drain terminal is coupled to a bit line, and the source terminal is coupled to a first node, wherein the floating gate is a first polysilicon layer;
• a select transistor, deposited in the P-well and comprising a gate terminal, a drain terminal, and a source terminal, wherein the gate terminal is coupled to a select gate, the drain terminal is coupled to the first node, and the source terminal is coupled to a source line, wherein the select gate is coupled to a word line, wherein the floating-gate transistor and the select transistor are N-type transistors;
• and
• a coupling structure, formed by extending the first polysilicon layer to overlap a control gate, wherein the control gate is a P-type doped region in an N-well, wherein the control gate is coupled to a control line.