One transistor and one ferroelectric capacitor memory cells in diagonal arrangements

A memory device, comprising:

• a transistor;
• and
• a ferroelectric capacitor comprising a first capacitor electrode, a second capacitor electrode, and a ferroelectric material between the first and second capacitor electrodes,
• wherein:
• the transistor includes a fin of a semiconductor material, the fin extending away from a base,
• the transistor is coupled to the ferroelectric capacitor,
• a gate terminal of the transistor is coupled to a wordline (WL), and
• a projection of the WL on a plane parallel to the base is at an angle between 5 and 45 degrees with respect to a projection of the fin on the plane.

A method of operating a memory device comprising an access transistor and a ferroelectric capacitor, the method comprising:

• driving a wordline (WL), coupled to a gate terminal of the access transistor, to cause the access transistor to turn on;
• and
• programming the ferroelectric capacitor by, when the access transistor is turned on, driving a bitline (BL) coupled to a first source/drain (S/D) terminal of the access transistor to charge or discharge an intermediate node coupled to a second S/D terminal of the access transistor, wherein the ferroelectric capacitor is coupled to and programmable according to a charge on the intermediate node,
• wherein the access transistor includes a fin of a semiconductor material, and
• wherein:
• either a projection of the BL on a plane parallel to a substrate over which the memory device is provided is at an angle between 5 and 45 degrees with respect to a projection of the fin on the plane,
• or a projection of the WL on said plane is at an angle between 5 and 45 degrees with respect to the projection of the fin on the plane.

A method of operating a memory device comprising an access transistor and a ferroelectric capacitor provided, the method comprising:

• driving a wordline (WL), coupled to a gate terminal of the access transistor, to cause the access transistor to turn on and to cause a current on a bitline (BL) through the access transistor, wherein the access transistor and the ferroelectric capacitor are coupled in electrical series by having one capacitor electrode of the ferroelectric capacitor being coupled to a source terminal or a drain terminal of the access transistor;
• driving a plateline (PL) coupled to another capacitor electrode of the ferroelectric capacitor to set a polarization state of the ferroelectric capacitor to a predefined logic state;
• and
• reading the ferroelectric capacitor by sensing the current on the BL to determine a logic state that was programmed in the ferroelectric capacitor prior to the polarization state of the ferroelectric capacitor being set to the predefined logic state,
• wherein the access transistor includes a fin of a semiconductor material, and
• wherein:
• either a projection of the BL on a plane parallel to a substrate over which the memory device is provided is at an angle between 5 and 45 degrees with respect to a projection of the fin on said plane,
• or a projection of the WL on said plane is at an angle between 5 and 45 degrees with respect to the projection of the fin on said plane.