Anti-fuse with reduced programming voltage

A semiconductor device having transistors and anti-fuses integrated thereon, comprising:

• a transistor region including a defect free monocrystalline strained semiconductor material formed over a semiconductor layer to form a device channel for a transistor;
• an anti-fuse region including:
• an oxidized surface of the semiconductor layer in the anti-fuse region forming an oxide layer having a thickness extending into the semiconductor layer in the anti-fuse region;
• a defective semiconductor layer epitaxially grown on the oxidized surface in the anti-fuse region;
• and
• gate structures formed in the transistor region and in the anti-fuse region, wherein the defective semiconductor layer is programmable by an applied field on the gate structures in the anti-fuse region.

A method for integrating transistors and anti-fuses on a device, comprising:

• epitaxially growing a semiconductor layer on a substrate;
• forming an oxide on an anti-fuse region of the semiconductor layer;
• growing a semiconductor material over the semiconductor layer to form an epitaxial semiconductor layer in a transistor region and a defective semiconductor layer in the anti-fuse region;
• and
• forming transistor devices in the transistor region and anti-fuse devices in the anti-fuse region wherein the defective semiconductor layer is programmable by an applied field.