FinFET SRAM Having Discontinuous PMOS Fin Lines
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines.
Claims20
A device, comprising:
- a static random access memory (SRAM) cells array that includes:
- a first type well, a second type well disposed adjacent to the first type well in a first direction, a plurality of elongated first fin structures that each extend in a second direction, wherein the first fin structures are disposed over the first type well;
- and
- a non-SRAM cells array that includes a plurality of elongated second fin structures that each extend in the second direction, wherein the second fin structures each have a substantially longer dimension in the second direction than each of the first fin structures.
A device, comprising:
- a plurality of static random access memory (SRAM) cells that are arranged into a first column that extends in a first direction in a top view;
- and
- a plurality of non-SRAM cells that are arranged into a second column that extends in the first direction in the top view;
- wherein:
- the SRAM cells include a plurality of first fin structures that each extends partially through two of the SRAM cells in the top view;
- and
- the non-SRAM cells include a plurality of second fin structures that each extends through three or more of the non-SRAM cells in the top view.
A device, comprising:
- a static random access memory (SRAM) that includes pull-up (PU) transistors, pass-gate (PG) transistors, and pull-down (PD) transistors, wherein:
- the PU transistors include a plurality of first fin structures, the PG transistors or the PD transistors includes a plurality of second fin structures;
- and
- a plurality of non-SRAM that include a plurality of third fin structures;
- wherein:
- the PU transistors include a plurality of first fin structures;
- the PG transistors or the PD transistors includes a plurality of second fin structures that are substantially longer than the first fin structures;
- and
- the third fin structures are substantially longer than the first fin structures.
Dependencies are inferred from the claim text.