Two transistor memory cell using stacked thin-film transistors

A memory cell, comprising:

• a substrate;
• a first thin-film transistor (TFT) in a back end of line (BEOL) stack above the substrate;
• and
• a second TFT, coupled to the first TFT, in the BEOL stack,
• wherein the second TFT is further away from the substrate than the first TFT.

A memory array, comprising:

• a plurality of memory cells arranged in rows and columns, individual ones of the memory cells including:
• an access thin-film transistor (TFT), and
• a gain TFT,
• wherein:
• a first source/drain (S/D) electrode of the access TFT is coupled to a gate electrode of the gain TFT,
• the access TFT is in a first layer over a substrate, and
• the gain TFT is in a second layer over the substrate, the first layer being between the substrate and the second layer;
• and
• for the memory cells arranged in a row i, a respective write wordline (WWLi), coupled to a gate electrode of the access TFT of individual ones of the memory cells in the row i.

A computing device, comprising:

• a circuit board;
• and
• a device coupled to the circuit board, wherein the device includes one or more of two-transistor (2T) memory cells, individual ones of the 2T memory cells including:
• an access thin-film transistor (TFT) in a back end of line (BEOL) stack above a substrate, and
• a gain TFT, coupled to the access TFT, in the BEOL stack,
• wherein the gain TFT is further away from the substrate than the access TFT.