Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor
AssigneeZeno Semiconductor, Inc.
InventorYuniarto Widjaja
Life of this patent
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Abstract
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
Claims21
1-19. (canceled)
A semiconductor memory array comprising:
- a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises:
- a plurality of bipolar devices;
- a common base region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell;
- wherein adjacent ones of each of said bipolar devices are separated by a conductive region having a second conductivity type;
- and
- wherein said base region is shared among said plurality of bipolar devices.
The semiconductor memory array of 25, wherein the fin structure further includes said conductive region or regions.
A semiconductor memory array comprising:
- a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises:
- a plurality of bipolar devices;
- a common base region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell;
- wherein adjacent ones of each of said bipolar devices are separated by a conductive region having a second conductivity type;
- and
- wherein a current flowing through each of said bipolar devices is a function of said charge stored in said common base region.
A semiconductor memory array comprising:
- a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises:
- a plurality of floating body transistors;
- a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell;
- and
- a plurality of conductive regions of a second conductivity type,
- wherein adjacent ones of each of said plurality of floating body transistors are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions.
The semiconductor memory array of 38, wherein the fin structure further includes the plurality of conductive regions.
Dependencies are inferred from the claim text.