Semiconductor devices

A semiconductor device comprising:

• a first wire pattern extending in a first direction on a substrate;
• a second wire pattern on the first wire pattern, wherein the second wire pattern is spaced apart from the first wire pattern and extends in the first direction;
• first, second, and third gate structures that are spaced apart from each other in the first direction and at least partially surround the first wire pattern and the second wire pattern;
• a first source/drain region between the first gate structure and the second gate structure, wherein the first source/drain region is on the first wire pattern and extends through the second wire pattern;
• a second source/drain region between the first gate structure and the third gate structure, wherein the second source/drain region extends through the first and second wire patterns;
• a first spacer between the first source/drain region and the substrate;
• a first source/drain contact on the first source/drain region;
• and
• a second spacer between the first source/drain contact and the first gate structure,
• wherein the first spacer comprises a material that the second spacer comprises.

A semiconductor device comprising:

• a first wire pattern extending in a first direction on a substrate;
• a second wire pattern on the first wire pattern, wherein the second wire pattern is spaced apart from the first wire pattern and extends in the first direction;
• a third wire pattern between the first and second wire patterns, wherein the third wire pattern is spaced apart from the first and second wire patterns and extends in the first direction;
• first, second and third gate structures that are spaced apart from each other in the first direction and at least partially surround the first, second and third wire patterns;
• a first source/drain region between the first and second gate structures, wherein the first source/drain region is on the first wire pattern and extends through the second and third wire patterns;
• a second source/drain region between the first and third gate structures, wherein the second source/drain region extends through the first, second and third wire patterns;
• and
• a first spacer at least partially surrounding the first wire pattern and being between a bottom surface of the first source/drain region and the substrate,
• wherein the second gate structure and the first source/drain region define a gate structure and a source/drain region of a first transistor, respectively, and the third gate structure and the second source/drain region define a gate structure and a source/drain region of a second transistor, respectively, and
• wherein the first and second transistors have an same conductivity type.