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US 2020/0091150 A1Published application
Semiconductor Device and Fabricating the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Ting-Hung Hsu
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Abstract
An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.
Claims20
A device comprising:
- a first fin structure disposed on a substrate, the first fin structure defining a first channel region, the first fin structure including:
- a first semiconductor material layer;
- a second semiconductor material layer disposed directly on the first semiconductor material layer, the second semiconductor material layer being different than the first semiconductor material layer and having a top surface facing away from the substrate, the top surface of the second semiconductor material layer extending to a first height;
- a first source/drain feature and a second source/drain feature disposed over the substrate;
- a first nanowire disposed over the first fin structure and defining a second channel region, the first nanowire extending between the first and second source/drain features;
- a shallow trench isolation structure disposed on the substrate and having a top surface extending to a second height that is different than the first height, the first fin structure at least partially embedded in the shallow trench isolation structure;
- a gate dielectric layer disposed directly on the top surface of the second semiconductor material layer;
- and
- a gate electrode layer disposed over the gate dielectric layer.
6 more elements
A device comprising:
- a first fin structure disposed over a substrate, the first fin structure defining a first channel region and formed of a first semiconductor material;
- a first nanowire disposed over the first fin structure, the first nanowire defining a second channel region and formed of a second semiconductor material that is different from the first semiconductor material;
- a second fin structure disposed over the substrate, the second fin structure defining a third channel region and formed of the first semiconductor material;
- a second nanowire disposed over the second fin structure, the second nanowire defining a fourth channel and formed of a third semiconductor material that is different from the second semiconductor material;
- and
- a fourth semiconductor material disposed directly on the first fin structure, the fourth semiconductor material being different than the third semiconductor material.
3 more elements
A device comprising:
- a dielectric isolation structure disposed on a substrate and extending to a first height over the substrate;
- a first fin structure extending to a second height over the substrate that is different than the first height, the first fin structure having a channel region and being formed of a first semiconductor material layer;
- a second fin structure extending to a third height over the substrate that is different than the second height, the second fin structure having a second channel region and being formed of the first semiconductor material layer;
- a second semiconductor material layer disposed directly on the first fin structure, the second semiconductor material layer being different than the first semiconductor material layer;
- a first nanowire disposed over the first fin structure, the first nanowire including a third channel region;
- a gate dielectric layer disposed around the first nanowire;
- and
- a gate electrode layer disposed around the gate dielectric layer.
5 more elements
Dependencies are inferred from the claim text.