Silicon carbide mosfet with source ballasting

A method for making an integrated device that includes a plurality of planar MOSFETs, comprising:

• a) providing a silicon carbide substrate composition of a first conductivity type;
• b) forming a plurality of doped body regions of a second conductivity type that is opposite the first conductivity type formed in an upper portion of the substrate;
• c) forming a plurality of doped source regions of the first conductivity type, wherein each of the plurality of doped source regions is formed in an upper portion of each of the plurality of body regions;
• d) forming a first contact region in a first source region of the plurality of source regions and forming a second contact region in a second source region of the plurality of source regions, wherein the first and second contact regions have respective portions of the source region doped with the second conductivity type, wherein the first and second contact regions are separated by a JFET region, wherein the JFET region is longer in one planar dimension than the other, wherein the first and second contact regions are separated by the longer planar dimension, wherein the JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region;
• e) forming an insulating layer on top of the silicon carbide substrate;
• f) forming an electrically conductive layer formed on the insulating layer and having openings corresponding to openings in underlying portions of the insulating over the contact regions.