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US 2020/0091137 A1Published application
Electrostatic discharge handling for lateral transistor devices
AssigneeSemiconductor Components Industries, LLC
InventorHan-Chung TAI
Life of this patent
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Abstract
A semiconductor transistor device includes a source region, a gate region having a p-type gate region and an n-type gate region, and a drain region having a p-type drain region and an n-type drain region. The p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region are positioned to provide, in response to an electrostatic discharge (ESD) voltage, a drain-to-gate ESD current path to at least partially discharge the ESD voltage.
Claims20
A semiconductor transistor device, comprising:
- a source region;
- a gate region having a p-type gate region and an n-type gate region;
- a drain region having a p-type drain region and an n-type drain region;
- a p-well formed at least partially under the gate region, and electrically shorted to the p-type gate region during an electrostatic discharge (ESD);
- and
- an n-well formed under the source region, the gate region, the p-well, and the drain region, and electrically shorted to the n-type drain region during the ESD,
- wherein the p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region are positioned to provide, in response to an ESD voltage, a drain-to-gate ESD current path to at least partially discharge the ESD voltage.
4 more elements
A semiconductor transistor device, comprising:
- a substrate of a first conductivity type;
- a first well region of a second conductivity type formed in the substrate;
- a source region of the second conductivity type formed in the first well region;
- a second well region of the first conductivity type formed in the first well region;
- a first gate region having the first conductivity type and formed in the second well region as part of a gate region;
- a second gate region having the second conductivity type and formed in the second well region as part of the gate region;
- a first drain region having the second conductivity type and formed in the first well region as part of a drain region;
- and
- a second drain region having the first conductivity type and formed in the first well region as part of the drain region,
- wherein at least the second drain region, the first well region, the second well region, and the second gate region form a structure that provides, in response to voltage induced by electrostatic discharge (ESD), a drain-to-gate ESD current path.
7 more elements
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Dependencies are inferred from the claim text.