Memory circuit layout method

A method comprising:

• placing a first rectangular oxide diffusion (OD) layout pattern in a layout design, the layout design corresponding to a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell of a memory circuit, the first rectangular OD layout pattern extending along a first direction and having a first source portion shared between the first memory cell and the second memory cell;
• placing a second rectangular OD layout pattern in the layout design, the second rectangular OD layout pattern extending along the first direction and having a second source portion shared between the third memory cell and the fourth memory cell;
• and
• placing a first rectangular conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure, extending along a second direction, and overlapping the first source portion and the second source portion,
• wherein the method is wholly or partially performed by using a hardware processor.

A method comprising:

• placing a first oxide diffusion (OD) layout pattern in a layout design of a memory circuit, the first OD layout pattern corresponding to a first active structure of first and second memory cells of the memory circuit, extending along a first direction, and having a first source portion shared between the first and second memory cells;
• placing a second OD layout pattern in the layout design, the second OD layout pattern corresponding to a second active structure of third and fourth memory cells of the memory circuit, extending along the first direction, and having a second source portion shared between the third and fourth memory cells;
• placing first and second gate layout patterns in the layout diagram, the first and second gate layout patterns corresponding to respective first and second gate structures of the memory circuit, extending along a second direction, and each overlapping each of the first and second OD layout patterns;
• and
• placing a first conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure of the memory circuit, extending along the second direction, and overlapping each of the first and second source portions,
• wherein
• the first conductive structure is positioned above the first and second active structures and between the first and second gate structures, and
• the method is wholly or partially performed by using a hardware processor.