Semiconductor package and manufacturing method thereof

A manufacturing method of a semiconductor package, comprising:

• providing a first chip, wherein the first chip comprises a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface and a plurality of through holes extending from the first back surface towards the first active surface;
• forming a plurality of through silicon vias in the through holes of the first chip;
• forming a first circuit structure on the first back surface of the first chip to electrically connect the through silicon vias;
• disposing a second chip on the first circuit structure, wherein the second chip comprises a second active surface facing towards the first back surface of the first chip, and the second chip is electrically connected to the first chip;
• and
• forming a second encapsulant on the first circuit structure to laterally encapsulate the second chip.

A manufacturing method of a semiconductor package, comprising:

• providing a plurality of first chips, each of the first chips comprising a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface and a plurality of through holes extending from the first back surface towards the first active surface;
• forming a plurality of through silicon vias in the through holes of the first chip;
• forming a first circuit structure on the first back surface of the first chip to electrically connect the through silicon vias;
• providing a carrier;
• providing at least one insulator;
• bonding the carrier, the insulator, and the first chips with the through silicon vias and the first circuit structure, wherein the insulator is disposed between the carrier and the first chips, the first active surfaces of the first chips facing towards the insulator, and the first chips disposed on the carrier are physically separated from each other;
• forming a first encapsulant on the carrier, wherein the first encapsulant laterally encapsulates the first chips;
• and
• forming a second circuit structure on the first encapsulant.