Stacked semiconductor chips having transistor in a boundary region
AssigneeSamsung Electronics Co., Ltd.
InventorSang Eun LEE
Life of this patent
Estimating the term…
Abstract
A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a first semiconductor chip which includes a first region, a second region, and a boundary region between the first region and the second region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is overlapping the first region and a part of the boundary region, and not overlapping the second region, wherein a first circuit element is disposed in the first region and a second circuit element is disposed in the boundary region, and wherein second circuit element stress tolerance is greater than first circuit element stress tolerance.
Claims21
1-20. (canceled)
A semiconductor package comprising:
- a first semiconductor chip which comprises a first region, a second region, and a boundary region between the first region and the second region;
- and
- a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is overlapping the first region and a part of the boundary region, and not overlapping the second region,
- wherein a plurality of first transistors are disposed in the boundary region,
- wherein a plurality of second transistors are disposed in the first region,
- wherein first sources and drains of the plurality of first transistors are aligned in the same direction as each other, and
- wherein second sources and drains of the plurality of second transistors are aligned in different directions.
A semiconductor package comprising:
- a first semiconductor chip which comprises a first region, a second region, and a boundary region between the first region and the second region;
- and
- a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is overlapping the first region and a part of the boundary region, and not overlapping the second region,
- wherein a plurality of first transistors are disposed in the second region,
- wherein a plurality of second transistors are disposed in the first region,
- wherein first sources and drains of the plurality of first transistors are aligned in the same direction as each other, and
- wherein second sources and drains of the plurality of second transistors are aligned in different directions.
A semiconductor package comprising:
- a first semiconductor chip which comprises a first region, a second region, and a boundary region between the first region and the second region;
- and
- a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is overlapping the first region and a part of the boundary region, and not overlapping the second region,
- wherein a first circuit element is disposed in the first region, a second circuit element is disposed in the boundary region, and a third circuit element is disposed in the second region,
- wherein the first circuit element comprises an active element, and
- wherein third circuit element stress tolerance is greater than first circuit element stress tolerance and is less than second circuit element stress tolerance.
Dependencies are inferred from the claim text.