Pad structure and manufacturing method thereof in semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-shu Huang, MING-CHYI Liu
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Abstract
A semiconductor device includes a substrate, a conductive pad region electrically coupled to the substrate, a first dielectric layer over the conductive pad region, and a passivation layer over the first dielectric layer, wherein the passivation layer includes a laterally-extending portion covering the first dielectric layer and a vertically-extending portion on a sidewall of the first dielectric layer. The laterally-extending portion and the vertically-extending portion of the passivation layer are joined along a vertically-extending boundary.
Claims20
A semiconductor device, comprising:
- a substrate;
- a conductive pad region electrically coupled to the substrate;
- a first dielectric layer over the conductive pad region;
- and
- a passivation layer over the first dielectric layer, wherein the passivation layer comprises a laterally-extending portion covering the first dielectric layer and a vertically-extending portion on a sidewall of the first dielectric layer, and wherein the laterally-extending portion and the vertically-extending portion of the passivation layer are joined along a vertically-extending boundary.
A semiconductor structure, comprising:
- a memory cell;
- and
- a pad structure electrically coupled to the memory cell, the pad structure comprising:
- a conductive pad region over the memory cell;
- a first dielectric layer disposed over the conductive pad region;
- and
- a first passivation layer laterally surrounded by the first dielectric layer and exposing an area of the conductive pad region, wherein a vertical portion of the first passivation layer comprises a substantially consistent thickness, and the vertical portion covers a sidewall of the first dielectric layer and defines the exposed area of the conductive pad region.
A semiconductor structure, comprising:
- a memory cell;
- and
- a redistribution layer electrically coupled to the memory cell, wherein the redistribution layer comprises a pad structure on a topmost layer of the redistribution layer, the pad structure comprising:
- a conductive pad region resting on an inter-metal dielectric (IMD) layer of the redistribution layer;
- a protection region over and partially exposing the conductive pad region, the protection region comprising a first hardness greater than a second hardness of the conductive pad region;
- a dielectric layer stack disposed over the conductive pad region, the protection region and the IMD layer;
- a passivation layer extending over the dielectric layer stack and exposing an area of the conductive pad region, wherein a vertical portion of the passivation layer comprises a substantially consistent thickness, and the vertical portion covers a sidewall of the dielectric layer stack and defines the exposed area of the conductive pad region;
- and
- a conductive plug electrically coupled to the conductive pad region and laterally surrounded by the passivation layer.
Dependencies are inferred from the claim text.