Three-dimensional semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-woo KIM, Joon-sung LIM, Jang-gn YUN, Sung-min HWANG
Life of this patent
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Abstract
A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.
Claims21
-20. (canceled)
A three-dimensional (3D) semiconductor device, comprising:
- a substrate;
- a peripheral logic structure on the substrate and including wiring layers and a peripheral insulating layer for insulating the wiring layers;
- a semiconductor layer on the peripheral logic structure;
- a stacked structure including electrodes vertically stacked on the semiconductor layer;
- a vertical structure penetrating the stacked structure;
- and
- four or more insulating layers between the substrate and the semiconductor layer,
- wherein at least one of the four or more insulating layers is a porous layer that is more porous than the peripheral insulating layer.
A three-dimensional (3D) semiconductor device, comprising:
- a substrate;
- a peripheral circuit region on the substrate, the peripheral circuit region including a peripheral logic structure including wiring layers and a peripheral insulating layer for insulating the wiring layers;
- a semiconductor layer on the peripheral circuit region;
- a cell array structure on the semiconductor layer, the cell array structure having a 3D memory cell array;
- and
- three or more insulating layers between the substrate and a lowermost wiring layer closest to the substrate among the wiring layers under the semiconductor layer.
A three-dimensional (3D) semiconductor device, comprising:
- a substrate;
- a peripheral logic structure on the substrate, the peripheral logic structure including wiring layers and a peripheral insulating layer for insulating the wiring layers;
- a polysilicon layer on the peripheral logic structure;
- a stacked structure including electrodes vertically stacked on the polysilicon layer;
- a vertical structure penetrating the stacked structure;
- and
- four or more insulating layers between the substrate and the polysilicon layer,
- wherein at least one of the four or more insulating layers is a porous layer that is more porous than the peripheral insulating layer,
- wherein the porous layer is between the substrate and a lowermost wiring layer closest to the substrate among the wiring layers under the polysilicon layer.
Dependencies are inferred from the claim text.