Controlling warp in semiconductor laminated substrates with conductive material layout and orientation

A laminated structure for electrically connecting to one or more semiconductor chips comprising:

• one or more parallel upper layers on an upper side of and parallel to a flat reference plane, at least one of the upper layers being a conductive material patterned with a uniform thickness disposed on an upper flat layer of non-conducting material;
• one or more parallel lower layers on a lower side of and parallel to the flat reference plane, at least one of the lower layers being the conductive material patterned with the uniformed thickness disposed on a lower flat layer of the non-conducting material, a selected upper layer and a selected lower layer selected as a corresponding pair of layers, and one or more upper tile subareas on the selected upper layer and one or more lower tile subareas on the selected lower layer, the upper and lower tile subareas being corresponding tile subareas when the upper and lower tile subareas are within a same vertical projection;
• an upper line sub-pattern being the conductive material patterned on the upper tile subarea, the upper line sub-pattern having an upper sub-pattern area that is an upper percentage area of the upper tile subarea and the upper sub-pattern area having an upper resultant orientation;
• a lower line sub-pattern being the conductive material patterned on the lower tile subarea, the lower line sub-pattern having a lower sub-pattern area that is a lower percentage area of the lower tile subarea and the lower sub-pattern area having a lower resultant orientation,
• wherein the upper percentage area equals the lower percentage area within an area tolerance and the upper resultant orientation equals the lower resultant orientation within an orientation tolerance, so the corresponding tile subareas deflect in the same amount and direction within a deflection tolerance as the laminated structure changes temperature.