Semiconductor device including gate pattern having pad region

A semiconductor device comprising:

• a first gate pattern over a lower structure;
• a second gate pattern over the first gate pattern;
• and
• an interlayer insulation layer between the first gate pattern and the second gate pattern,
• wherein the first gate pattern includes a gate electrode region overlapping with the second gate pattern, and a gate pad region extending from the gate electrode region,
• the gate pad region includes a first pad region having a thickness greater than a thickness of the gate electrode region,
• the first pad region includes a lower region and an upper region on the lower region, and
• the lower region includes a lower outer side surface having a convex shape.

A semiconductor device comprising:

• a lower structure;
• gate patterns spaced apart from each other in a direction perpendicular to an upper surface of the lower structure, the gate patterns including intermediate gate patterns;
• and
• a vertical channel semiconductor layer having a side surface facing the intermediate gate patterns,
• wherein each of the intermediate gate patterns includes a gate electrode region overlapping with a gate pattern from among the gate patterns positioned at a relatively upper portion, and a gate pad region extending from the gate electrode region,
• the gate pad region includes a first pad region, and a second pad region between the gate electrode region and the first pad region,
• the first pad region has a thickness greater than a thickness of the gate electrode region and a thickness of the second pad region,
• the first pad region includes a lower outer side surface, an upper outer side surface, and a boundary portion between the upper outer side surface and the lower outer side surface, and
• a connection portion of a bottom surface of the first pad region and the lower outer side surface of the first pad region has a rounded shape.