Chip scale package structure and method of forming the same

A semiconductor package structure, comprising:

• a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface;
• a first protective insulating layer covering the first surface of the semiconductor die;
• a redistribution layer (RDL) structure electrically coupled to the semiconductor die and surrounded by the first protective insulating layer;
• a second protective insulating layer covering the second surface and the third surface of the semiconductor die;
• a first passivation layer covering the first protective insulating layer and the RDL structure;
• and
• at least one conductive structure passing through the first passivation layer and electrically coupled to the RDL structure.

A method of forming a semiconductor package structure, comprising:

• providing a semiconductor die, wherein the semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface;
• forming a redistribution layer (RDL) structure on the first surface of the semiconductor die, wherein the RDL structure is electrically coupled to the semiconductor die;
• forming a first protective insulating layer to cover the first surface and the third surface of the semiconductor die and to surround the RDL structure;
• covering the first protective insulating layer and the RDL structure with a first passivation layer;
• and
• forming at least one conductive structure passing through the first passivation layer to be electrically coupled to the RDL structure.

A method of forming a semiconductor package structure, comprising:

• providing a semiconductor die, wherein the semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface;
• forming a redistribution layer (RDL) structure on the first surface of the semiconductor die, wherein the RDL structure is electrically coupled to the semiconductor die;
• forming a first protective insulating layer to cover the first surface of the semiconductor die and to surround the RDL structure;
• forming a second protective insulating layer to cover the second surface and the third surface of the semiconductor die;
• forming a first passivation layer to cover the first protective insulating layer and the RDL structure;
• and
• forming at least one conductive structure passing through the first passivation layer to be electrically coupled to the RDL structure.