Selective Formation of Conductor Nanowires
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChao-Hsien Peng, Hsiang-Huan Lee, Shau-Lin Shue
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Abstract
A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.
Claims20
An integrated circuit structure comprising:
- a first metal line over a semiconductor substrate, the first metal line being ring-shaped in a top-down view, the first metal line comprising a first inner sidewall and a second inner sidewall opposite the first inner sidewall, wherein a distance between a top portion of the first inner sidewall and a top portion of the second inner sidewall is less than a distance between a bottom portion of the first inner sidewall and a bottom portion of the second inner sidewall;
- a dielectric layer surrounding the first metal line, wherein a top surface of the dielectric layer is disposed above a top surface of the first metal line;
- and
- a conductive via extending through the dielectric layer and connected to the first metal line.
An integrated circuit structure comprising:
- an etch stop layer over an inter-layer dielectric;
- a first metal line over the etch stop layer, the first metal line having a first sidewall and a second sidewall opposite the first sidewall;
- a second metal line over the etch stop layer and adjacent the first metal line, the second metal line having a third sidewall and a fourth sidewall opposite the third sidewall, wherein the first sidewall faces the third sidewall, wherein a bottom portion of the first sidewall is separated from a bottom portion of the third sidewall by a first positive distance, wherein a top portion of the first sidewall is separated from a top portion of the third sidewall by a second positive distance, and wherein the second positive distance is greater than the first positive distance;
- and
- a dielectric layer surrounding the first metal line and the second metal line.
An integrated circuit structure comprising:
- a first metal line comprising:
- a first tilted sidewall;
- and
- a second tilted sidewall opposite to the first tilted sidewall, wherein the second tilted sidewall is parallel to the first tilted sidewall;
- a first via over and in contact with a top surface of the first metal line;
- and
- an inter-layer dielectric surrounding the first tilted sidewall, the second tilted sidewall, and the first via.
Dependencies are inferred from the claim text.