Stacked through-silicon vias for multi-device packages
AssigneeIntel Corporation
InventorsBok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
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Abstract
Disclosed embodiments include a multi-chip package that includes a stacked through-silicon via in a first semiconductive device, and the first semiconductive device is face-to-face coupled to a second semiconductive device by the stacked through-silicon via. The stacked through-silicon via includes a first portion that contacts a second portion, and the first portion emerges from an active semiconductive region of the first semiconductive device adjacent a keep-out region.
Claims27
A semiconductor device, comprising:
- a semiconductive substrate including a first surface and a backside surface opposite the first surface;
- a stacked through-silicon via in the semi conductive substrate, including a stacked through-silicon via first portion that communicates to -the first surface and a stacked through-silicon via second portion that communicates to the backside surface, wherein the stacked through-silicon via first portion contacts the stacked through-silicon via second portion, and wherein the stacked through-silicon via first portion has a smaller lateral dimension than the stacked through-silicon via second portion;
- at least one active semiconductive region derived from the first surface;
- and
- a keep-out region on the first surface that surrounds and is adjacent the stacked through-silicon via first portion.
A semiconductor device, comprising:
- a semiconductive substrate including a first surface and a backside surface opposite the first surface;
- a stacked through-silicon via in the semi conductive substrate, including a stacked through-silicon via first portion that communicates to the first surface and a stacked through-silicon via second portion that communicates to the backside surface, wherein the stacked through-silicon via first portion contacts the stacked through-silicon via second portion, and wherein the stacked through-silicon via first portion has a smaller lateral dimension than the stacked through-silicon via second portion;
- an isolated stacked through-silicon via first portion that communicates to the first surface, wherein the isolated stacked through-silicon via first portion is within the lateral dimension of the stacked through-silicon via second portion and is isolated from the stacked through-silicon via first portion and the stacked through silicon-via second portion, wherein the stacked through-silicon via is selected from the group consisting of power, ground and signal stacked through-silicon vias, and wherein the isolated stacked through-silicon via first portion is selected from the group consisting of power and ground isolated stacked through-silicon via first portion that is different from the stacked through-silicon via;
- at least one active semiconductive region derived from the first surface;
- and
- a keep-out region on the first surface that surrounds and is adjacent the stacked through-silicon via first portion.
A process of assembling a stacked through-silicon via device, comprising:
- forming a recess in a semiconductive device substrate from a backside surface;
- forming a recess in the semiconductive device substrate from a first surface to open the recess from the backside surface;
- form a stacked through-silicon via first portion in the recess at the first surface and a stacked through-silicon via second portion in the recess at the backside surface to contact the stacked through-silicon via first portion;
- and
- form active semiconductive regions on the first surface with keep-out regions adjacent the stacked through-silicon via first portion to achieve a semiconductive device.
Dependencies are inferred from the claim text.