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US 2020/0091027 A1Published application
Integrated Circuit Packages and Methods for Forming the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
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Abstract
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
Claims20
A method comprising:
- forming a solder region on a wafer, wherein the wafer comprises a plurality of chips, with the solder region being in a first chip of the plurality of chips;
- forming a dielectric layer to embed a portion of the solder region in the dielectric layer, wherein the dielectric layer comprises a first portion and a second portion;
- thinning the first portion of the dielectric layer without thinning the second portion of the dielectric layer;
- and
- sawing the wafer to separate the plurality of chips from each other, wherein the sawing comprises using a feature underlying the thinned first portion of the dielectric layer for alignment.
2 more elements
A method comprising:
- forming a first electrical connector and a second electrical connector on a first chip and a second chip of a wafer;
- molding the first electrical connector and the second electrical connector to be partially in a molding compound;
- performing a first sawing process to form a trench in the molding compound, wherein the trench comprises a first portion extending into the first chip, wherein after the first sawing process, a conductive feature is visible through a remaining portion of the molding compound directly underlying the trench;
- and
- after the first sawing process, performing a second sawing process to saw through a scribe line that separates the first chip and the second chip from each other, wherein in the second sawing process, the conductive feature is used as an alignment mark.
2 more elements
A method comprising:
- molding a wafer comprising a first chip and a second chip with a molding compound, wherein a solder region in the first chip is partially molded in the molding compound;
- performing a thinning process to thin the molding compound, until a feature underlying the molding compound is visible;
- and
- after the thinning process, performing a die-saw process to separate the first chip and the second chip from each other, wherein the feature is used as an alignment mark.
1 more element
Dependencies are inferred from the claim text.