Power Semiconductor Module Arrangement and Housing for a Power Semiconductor Arrangement

#The instant disclosure relates to a power semiconductor module arrangement and a housing for a power semiconductor module arrangement.

#Power semiconductor module arrangements often include a substrate within a housing. The substrate usually comprises a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer and a second metallization layer deposited on a second side of the substrate layer. A semiconductor arrangement including one or more controllable semiconductor elements (e.g., two IGBTs in a half-bridge configuration) may be arranged on the substrate. One or more contact elements, which allow for contacting such a semiconductor arrangement from outside the housing, are usually provided. Power semiconductor modules are known in which the contact elements are arranged on the substrate and protrude in a direction that is essentially perpendicular to the main surface of the substrate through a cover of the housing. The section of the contact elements which protrudes out of the housing may be mechanically and electrically coupled to a printed circuit board. Usually, the printed circuit board comprises through holes and the contact elements are inserted through the respective through holes. Such arrangements usually require an extensive developmental effort and a large number of manufacturing steps. Therefore, the costs for such arrangements are comparably high.

#There is a need for a power semiconductor module arrangement that requires reduced developmental effort and a reduced number of manufacturing steps and is therefore more cost-effective than conventional power semiconductor module arrangements.

#FIG. 1 is a cross-sectional view of a power semiconductor module arrangement.

#FIG. 2 schematically illustrates a semiconductor substrate in a housing with connection elements.

#FIGS. 3A and 3B schematically illustrate a pressfit connection.

#In the following detailed description, reference is made to the accompanying drawings. The drawings show specific examples in which the invention may be practiced. It is to be understood that the features and principles described with respect to the various examples may be combined with each other, unless specifically noted otherwise. In the description, as well as in the claims, designations of certain elements as “first element”, “second element”, “third element” etc. are not to be understood as enumerative. Instead, such designations serve solely to address different “elements”. That is, e.g., the existence of a “third element” does not require the existence of a “first element” and a “second element”. A semiconductor body as described herein may be made from (doped) semiconductor material and may be a semiconductor chip or may be included in a semiconductor chip. A semiconductor body has electrically connecting pads and includes at least one semiconductor element with electrodes.

#Referring to FIG. 1, a conventional power semiconductor module arrangement is illustrated. The power semiconductor module arrangement includes a substrate 10. The substrate 10 includes a dielectric insulation layer 11, a (structured) first metallization layer 111 arranged on a first side of the dielectric insulation layer 11, and a second metallization layer 112 arranged on a second side of the dielectric insulation layer 11. The dielectric insulation layer 11 is disposed between the first and the second metallization layer 111, 112. The substrate 10, however, may also include multiple dielectric insulation layers and metallization layers stacked alternatingly on each other, with buried metallization layers acting either as shielding layers or being part of the electronic circuit and electrically connected to other metallization layers by means of through contacts. A buried metallization layer in this context is a metallization layer that is arranged between two dielectric insulation layers.

#Again referring to FIG. 1, each of the first and second metallization layers 111, 112 may consist of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains solid during the operation of the power semiconductor module arrangement. The substrate 10 may be a ceramic substrate, that is, a substrate in which the dielectric insulation layer 11 is a ceramic, e.g., a thin ceramic layer. The ceramic may consist of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. The substrate 10 may be, e.g., a Direct Copper Bonding (DCB) substrate, a Direct Aluminum Bonding (DAB) substrate, or an Active Metal Brazing (AMB) substrate. Further, the substrate 10 may be an Insulated Metal Substrate (IMS). An Insulated Metal Substrate generally comprises a dielectric insulation layer 11 comprising (filled) materials such as epoxy resin or polyimide, for example. The material of the dielectric insulation layer 11 may be filled with ceramic particles, for example. Such particles may comprise, e.g., Si2O, Al2O3, AlN, or BrN and may have a diameter of between about 1 μm and about 50 μm. The first metallization layer 111 of an IMS may be a comparably thin copper layer (e.g., thickness of between 35 μm and 140 μm), and the second metallization layer 112 may be a comparably thick aluminum or copper layer (e.g., thickness of between 0.6 mm and 2.0 mm), for example. The substrate 10, however, may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulation layer 11. For instance, a non-ceramic dielectric insulation layer 11 may consist of or include a cured resin.