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US 2020/0091020 A1Published application
Pad structures in semiconductor devices
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsWANBING YI, LAIQIANG LUO, XINGYU CHEN, FAN ZHANG, JUAN BOON TAN
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Abstract
A semiconductor interconnect structure including a conductive layer, a plurality of interconnect vias and a pad is presented. The interconnect vias are formed over the conductive layer and the pad having a substantially flat surface is formed over the plurality of interconnect vias. The conductive layer may be a conductive line and/or a conductive plate connected to a conductive line.
Claims20
A semiconductor device comprising:
- a conductive layer;
- a plurality of interconnect vias over the conductive layer;
- and
- a probe pad having a substantially flat surface over the plurality of interconnect vias, wherein the plurality of interconnect vias is arranged in an array configuration and has substantially equal pitch between each interconnect via.
1 more element
(canceled)
(canceled)
A semiconductor device comprising:
- at least one conductive plate;
- an array of interconnect vias over the conductive plate, wherein the array of interconnect vias is arranged in a n×m matrix where n and m are integers of value 2 or more;
- and
- a probe pad over the array of interconnect vias, wherein the probe pad and the array of interconnect vias are formed of a same conductive material.
1 more element
(canceled)
A method of fabricating a pad structure comprising:
- providing a conductive layer;
- forming a dielectric layer over the conductive layer;
- forming a plurality of via openings in the dielectric layer over the conductive layer;
- depositing a conductive material in the plurality of via openings to form interconnect vias;
- and
- forming a pad over the plurality of interconnect vias.
3 more elements
Dependencies are inferred from the claim text.