Selective dual silicide formation using a maskless fabrication process flow
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMrunal A. Khaderbad, Pang-Yen Tsai, Yasutoshi Okuno
Life of this patent
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Abstract
A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.
Claims20
A method of fabricating a semiconductor device, comprising:
- selectively forming a first dielectric layer such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor, wherein the first type of transistor and the second type of transistor have different types of conductivity;
- selectively forming a first silicide layer such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor;
- removing the first dielectric layer;
- and
- forming a second silicide layer over the source/drain region of the first type of transistor.
A semiconductor device, comprising:
- an NFET that includes:
- a first source/drain region;
- a first silicide layer disposed over the first source/drain region, the first silicide layer having a first work function;
- and
- a first conductive contact disposed over the first silicide layer;
- and
- a PFET that includes:
- a second source/drain region;
- a second silicide layer disposed over the second source/drain region, the second silicide layer having a second work function that is higher than the first work function;
- and
- a second conductive contact disposed over the second silicide layer;
- wherein the first silicide layer has a more elevated position than the second silicide layer.
A semiconductor device, comprising:
- an NFET that includes:
- a first source/drain region;
- a first silicide layer disposed over the first source/drain region, the first silicide layer having a first work function;
- a first dielectric layer disposed over the first silicide layer;
- and
- a first conductive contact disposed over the first dielectric layer;
- and
- a PFET that includes:
- a second source/drain region;
- a second silicide layer disposed over the second source/drain region, the second silicide layer having a second work function that is greater than the first work function;
- a conductive layer disposed over the second silicide layer;
- a second dielectric layer disposed over the conductive layer;
- and
- a second conductive contact disposed over the second dielectric layer.
Dependencies are inferred from the claim text.