Nanosheet transistors with different gate dielectrics and workfunction metals

A method for forming a semiconductor device, comprising:

• patterning a stack of layers that includes silicon channel layers, sacrificial n-type doped silicon layers between the channel layers, and sacrificial carbon-doped silicon germanium diffusion barrier layers between the silicon channel layers and the sacrificial doped silicon layers, to form one or more device regions;
• recessing the sacrificial n-type doped silicon layers and the sacrificial carbon-doped silicon germanium diffusion barrier layers relative to the channel layers with distinct respective etches to produce a flat, continuous, and vertical surface from sidewalls of the first sacrificial layers and respective second sacrificial layers;
• forming inner spacers, in recesses formed by the recessing of the sacrificial n-type doped silicon layers and the sacrificial carbon-doped silicon germanium layers, that have flat, vertical sidewalls facing the sacrificial n-type doped silicon layers and the sacrificial carbon-doped silicon germanium layers;
• etching away the sacrificial n-type doped silicon layers and the sacrificial carbon-doped silicon germanium layers to leave the channel layers suspended.