Semiconductor device having planar transistor and finfet

A device, comprising:

• a first transistor comprising:
• an active region comprising a first channel region;
• a first source and a first drain in the active region of the first transistor and respectively on opposite sides of the first channel region;
• and
• a first gate structure over the first channel region;
• a first isolation structure surrounding the active region of the first transistor, wherein a top of the first isolation structure is substantially aligned with a top of the first channel region;
• a second transistor comprising:
• a second source and a second drain;
• a fin structure comprising a second channel region between the second source and the second drain, wherein a top of the second channel region is substantially aligned with the top of the first channel region;
• and
• a second gate structure over the second channel region;
• and
• a second isolation structure surrounding a bottom portion of the fin structure of the second transistor, wherein the top of the second channel region is higher than a top of the second isolation structure.

A device, comprising:

• a first transistor comprising:
• an active region comprising a first channel region;
• a first source and a first drain in the active region and respectively on opposite sides of the first channel region;
• and
• a first gate structure over the first channel region;
• a first isolation structure surrounding the active region of the first transistor, wherein a top of the first isolation structure is substantially aligned with a top of first channel region;
• a second transistor comprising:
• a second source and a second drain, wherein a bottom of the first drain is higher than a bottom of the second drain;
• a fin structure comprising a second channel region between the second source and the second drain;
• and
• a second gate structure over the second channel region;
• and
• a second isolation structure surrounding a bottom portion of the fin structure of the second transistor.