Simultaneous metal patterning for 3d interconnects
AssigneeApplied Materials, Inc.
InventorSuketu A. Parikh
Life of this patent
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Abstract
Processing methods may be performed to produce three-dimensional interconnects on a substrate. The methods may include forming a first metal interconnect layer over a semiconductor substrate. The methods may include forming a first dielectric layer over the first metal interconnect layer. The methods may include forming a second metal interconnect layer over the first dielectric layer. The methods may include forming a patterning mask overlying the second metal interconnect layer. The methods may also include simultaneously etching each of the first metal interconnect layer, the first dielectric layer, and the second metal interconnect layer to expose the substrate to produce a multilayer interconnect structure in a first lateral direction.
Claims20
A method of forming three-dimensional metal interconnects, the method comprising:
- forming a first metal interconnect layer over a semiconductor substrate;
- forming a first dielectric layer over the first metal interconnect layer;
- forming a second metal interconnect layer over the first dielectric layer;
- forming a patterning mask overlying the second metal interconnect layer;
- and
- simultaneously etching each of the first metal interconnect layer, the first dielectric layer, and the second metal interconnect layer to expose the substrate to produce a multilayer interconnect structure in a first lateral direction.
A method of forming three-dimensional metal interconnects, the method comprising:
- forming a first metal interconnect layer over a semiconductor substrate;
- forming a first dielectric layer over the first metal interconnect layer;
- forming a second metal interconnect layer over the first dielectric layer;
- forming a patterning mask overlying the second metal interconnect layer;
- simultaneously etching each of the first metal interconnect layer, the first dielectric layer, and the second metal interconnect layer in a first lateral direction to expose a region of the substrate;
- filling the exposed region with a low-k dielectric material to produce a structure;
- forming one or more vias through the structure;
- forming a first liner within each of the one or more vias;
- and
- selectively recessing the first liner to expose one of the first metal interconnect layer or the second metal interconnect layer.
Dependencies are inferred from the claim text.