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US 2020/0090993 A1Published application
Semiconductor device with reduced via resistance
AssigneeInternational Business Machines Corporation
InventorsConal E. Murray, Chih-Chao Yang
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Abstract
A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.
Claims10
A semiconductor interconnect structure comprising:
- a first electrically conductive structure of a first interconnect level, the first electrically conductive structure having a plurality of bottom portions;
- a dielectric capping layer, at least a portion of the dielectric capping layer being horizontally planar with and in contact with a first bottom portion of the plurality of bottom portions, the portion of the dielectric capping layer being between the first interconnect level and a second interconnect level that is below the first interconnect level;
- a second electrically conductive structure in the second interconnect level, the second electrically conductive structure being in electrical contact with a second bottom portion of the plurality of bottom portions, the second bottom portion being vertically offset with the first bottom portion such that the second bottom portion is closer to the second electrically conductive structure than the first bottom portion;
- and
- a portion of liner material separating, at least in part, the second bottom portion of the first electrically conductive structure from the second electrically conductive structure.
2 more elements
Dependencies are inferred from the claim text.