Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability

An interconnect stack comprising:

• a first dielectric layer;
• a first trench formed in the first dielectric layer;
• a first liner deposited in the first trench, wherein the first liner defines a second trench;
• a first conductive material in the second trench;
• a second dielectric layer deposited over the first dielectric layer and the first conductive material;
• a third trench that extends through the second dielectric layer and is over the first conductive material;
• a bottom surface of the third trench comprises at least a portion of the top surface of the first conductive material;
• and
• a second liner in the third trench;
• wherein the second liner is on sidewalls of the third trench;
• wherein the second liner is also on the portion of the top surface of the first conductive material;
• wherein the second liner that is on the portion of the top surface of the first conductive material functions as a cap region configured to counter electro-migration or surface migration at the top surface of the first conductive material;
• wherein a second conductive material is deposited in the first region of the third trench;
• wherein the second liner adheres a portion of the second conductive material to the second dielectric layer;
• and
• wherein a bottom surface of the second region of the third trench comprises a top surface of the second conductive material.