Gate driver circuit, level shifter, and display apparatus

A level shifter, wherein, the level shifter comprises a gate driver circuit, the gate driver circuit comprises:

• a potential enhancing unit, configured to divide a clock signal output by a timing sequence controller into two clock signal groups after the clock signal being potential enhanced by the potential enhancing unit, and correspondingly output the two clock signal groups to two shift register groups on a display panel, to drive the display panel to work;
• the two clock signal groups respectively comprising at least one sub-clock signal;
• a switch unit, connected in series between the potential enhancing unit and the shift registers at both ends of the display panel, and configured to correspondingly switch on or off according to a control signal received, to control to output or stop outputting the clock signal groups;
• a current detecting unit, connected in series between the potential enhancing unit and the switch unit, or in series between the switch unit and the shift registers at both ends of the display panel, configured to respectively detect output current of each sub-clock signal in the two clock signal groups, and feed back a plurality of current signals to the control unit;
• and
• a control unit, configured to receive the plurality of current signals output by the current detecting unit, and compare current values corresponding to the plurality of current signals with a preset current threshold respectively, when the current value of any one of the sub-clock signals in one of the clock signal groups is less than the preset current threshold, output a control signal to the switch unit, to control the switch unit to cut off the output of the clock signal group.

A display apparatus, wherein, the display apparatus comprises a level shift IC, the level shift IC comprises a gate driver circuit, the gate driver circuit comprises:

• a potential enhancing unit, configured to divide a clock signal output by a timing sequence controller into two clock signal groups after the clock signal being potential enhanced by the potential enhancing unit, and correspondingly output the two clock signal groups to two shift register groups on a display panel, to drive the display panel to work;
• the two clock signal groups respectively comprising at least one sub-clock signal;
• a switch unit, connected in series between the potential enhancing unit and the shift registers at both ends of the display panel, and configured to correspondingly switch on or off according to a control signal received, to control to output or stop outputting the clock signal groups;
• a current detecting unit, connected in series between the potential enhancing unit and the switch unit, or in series between the switch unit and the shift registers at both ends of the display panel, configured to respectively detect output current of each sub-clock signal in the two clock signal groups, and feed back a plurality of current signals to the control unit;
• and
• a control unit, configured to receive the plurality of current signals output by the current detecting unit, and compare current values corresponding to the plurality of current signals with a preset current threshold respectively, when the current value of any one of the sub-clock signals in one of the clock signal groups is less than the preset current threshold, output a control signal to the switch unit, to control the switch unit to cut off the output of the clock signal group.