Fuse latch of semiconductor device

A fuse latch of a semiconductor device comprising:

• first and second NMOS transistors, each of which is configured to receive a first control signal through its gate terminal and to transmit fuse cell data in response to the first control signal;
• a first inverter comprising a first PMOS transistor and a third NMOS transistor that are coupled in series between a power-supply voltage and a ground voltage, the first inverter configured to include an output node coupled to the first NMOS transistor and to include an input node coupled to the second NMOS transistor;
• a second inverter comprising a second PMOS transistor and a fourth NMOS transistor that are coupled in series between the power-supply voltage and the ground voltage, the second inverter configured to include an input node coupled to the output node of the first inverter and to include an output node coupled to the input node of the first inverter;
• a fifth NMOS transistor comprising a gate terminal coupled to the input node of the first inverter and coupled to the output node of the second inverter and comprising a first terminal coupled to a data output terminal;
• and
• a sixth NMOS transistor configured to receive a second control signal through its gate terminal and configured to selectively couple the ground voltage to a second terminal of the fifth NMOS transistor in response to the second control signal,
• wherein the first and second PMOS transistors are formed in a first active region, the first to fourth NMOS transistors are formed in a second active region located at one side of the first active region in a first direction, and the fifth and sixth transistors are formed in a third active region located at one side of the second active region in the first direction.