Semiconductor memory device

A semiconductor memory device comprising:

• a first semiconductor region of p-type;
• n word lines from a first word line to an nth word line stacked on the first semiconductor region in a first direction;
• a second semiconductor region of n-type;
• a semiconductor layer provided between the first semiconductor region and the second semiconductor region, the semiconductor layer extending in the first direction, and the semiconductor layer intersecting with the n word lines;
• a bit line electrically connected to the second semiconductor region;
• and
• a control circuit configured to perform a first verify operation and a second verify operation after the first verify operation,
• wherein, to verify whether or not a kth (4<k<n) memory cell provided in a region where a kth word line and the semiconductor layer intersect with each other has reached a desired threshold voltage,
• a first voltage is applied between the first semiconductor region and the second semiconductor region in the first verify operation, and
• a second voltage different from the first voltage is applied between the first semiconductor region and the second semiconductor region in the second verify operation.