Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorTakashi Maeda
Life of this patent
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Abstract
A semiconductor memory device according to an embodiment includes a string, a bit line, a well line, and a sequencer. The string includes first and second select transistors, and memory cell transistors using a ferroelectric material. The bit line and the well line are connected to the first and second select transistors, respectively. At a time in an erase verify operation, the sequencer is configured to apply a first voltage to the memory cell transistors, to apply a second voltage lower than the first voltage to the first select transistor, to apply a third voltage lower than the first voltage to the second select transistor, to apply a fourth voltage to the bit line, and to apply a fifth voltage higher than the fourth voltage to the well line.
Claims20
A semiconductor memory device comprising:
- a string including a first select transistor, a second select transistor, and a plurality of memory cell transistors connected in series between the first select transistor and the second select transistor, each of the memory cell transistors using a ferroelectric material for a memory layer;
- a bit line connected to the first select transistor;
- a well line connected to the second select transistor;
- and
- a sequencer,
- wherein at a first time instant in an erase verify operation after an erase operation with the string being selected, the sequencer is configured to apply a first voltage to a gate of the memory cell transistor, to apply a second voltage, which is lower than the first voltage, to a gate of the first select transistor, to apply a third voltage, which is lower than the first voltage, to a gate of the second select transistor, to apply a fourth voltage to the bit line, and to apply a fifth voltage, which is higher than the fourth voltage, to the well line.
Dependencies are inferred from the claim text.