Semiconductor memory device, memory system, and method
AssigneeToshiba Memory Corporation
InventorRui ITO
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a plurality of memory cells that include one or more pairs of reference cells that store reference data, and a circuit peripheral thereto. The memory cells are commonly connected to a word line and connected to a plurality of bit lines, respectively. The circuit is configured to apply a read voltage to the word line, cause sense nodes of bit lines connected to the reference memory cells of each pair to be electrically connected to each other, determine whether or not each of the plurality of reference memory cells is ON or OFF based on a voltage at a sense node of each of the plurality of bit lines, and update the read voltage based on the number of reference memory cells determined to be ON and the number thereof determined to be OFF.
Claims20
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells commonly connected to a word line and connected to a bit line, respectively, the plurality of memory cells including one or more pairs of reference memory cells that store reference data;
- and
- a circuit peripheral to the memory cell array and configured to, during a read operation:
- apply a read voltage to the word line;
- for each pair of reference memory cells, cause sense nodes of bit lines connected to the reference memory cells to be electrically connected to each other;
- determine whether each of the plurality of reference memory cells is in an ON state or an OFF state based on a voltage at a sense node of each of the plurality of bit lines;
- and
- update the read voltage based on the number of reference memory cells determined to be in the ON state and the number of reference memory cells determined to be in the OFF state.
A memory system comprising:
- a plurality of memory chips;
- and
- a memory controller communicable to a host and configured to control the plurality of memory chips based on a request from the host, wherein
- each of the plurality of memory chips comprising:
- a memory cell array including a plurality of memory cells commonly connected to a word line and connected to a plurality of bit lines, respectively, the plurality of memory cells including one or more pairs of reference memory cells that store reference data;
- and
- a circuit peripheral to the memory cell array and configured to, during a read operation:
- apply a read voltage to the word line;
- for each pair of reference memory cells, cause sense nodes of bit lines connected to the reference memory cells to be electrically connected to each other;
- determine whether or not each of the plurality of reference memory cells is in an ON state or an OFF state based on a voltage at a sense node of each of the plurality of bit lines;
- and
- update the read voltage based on the number of reference memory cells determined to be in the ON state and the number of reference memory cells determined to be in the OFF state.
A method of controlling a semiconductor memory device including a memory cell array including a plurality of memory cells commonly connected to a word line and connected to a bit line, respectively, the plurality of memory cells including one or more pairs of reference memory cells that store reference data, the method comprising, during a read operation:
- applying a read voltage to the word line;
- for each pair of reference memory cells, electrically connecting sense nodes of bit lines connected to the reference memory cells to each other;
- determining whether each of the plurality of reference memory cells is in an ON state or an OFF state based on a voltage at a sense node of each of the plurality of bit lines;
- and
- updating the read voltage based on the number of reference memory cells determined to be in the ON state and the number of reference memory cells determined to be in the OFF state.
Dependencies are inferred from the claim text.